1. Field of the Invention
The present invention relates to semiconductor structures and methods of forming semiconductor structures, and more particularly to isolation structures and methods of fabricating isolation structures.
2. Description of the Related Art
With advances associated with electronic products, semiconductor technology has been widely applied in manufacturing memories, central processing units (CPUs), liquid crystal displays (LCDs), light emission diodes (LEDs), laser diodes and other devices or chip sets. In order to achieve high-integration and high-speed goals, dimensions of semiconductor integrated circuits continue to shrink. Various materials and techniques have been proposed to achieve these integration and speed goals and to overcome manufacturing obstacles associated therewith. Due to high integration, electrical isolation between adjacent devices or circuits has increased in importance. To that end, shallow trench isolation (STI) structures have been used in this art.
FIGS. 1A-1B are schematic cross-sectional views showing a prior art process for removing a pad oxide layer formed over a substrate.
More specifically, FIG. 1A shows a shallow trench isolation structure in which a pad nitride layer has been removed. The prior art structure comprises a pad oxide layer 110 formed over the substrate 100. An opening (not shown) is formed within the pad oxide layer 110 and substrate 100. A substantially conformal liner layer 120 is formed within the opening. A high density plasma chemical vapor deposition (HDP CVD) oxide layer 130 is then formed within the opening, thereby filling the opening and forming a STI structure.
In the prior art process for the formation of the HDP CVD oxide 130, initially a thin region 130a of the HDP CVD oxide 130 is formed by a HDP CVD process without turning on bias power for bombardment before the formation of the bulk of the HDP CVD oxide layer 130. The thin region 130a must be form substantially conformal over the liner layer 120 without changing the profile of the opening so as to avoid difficulty of bulk filling. This region is illustrated by dashed lines. The process for the formation of the thin region 130a of the HDP CVD oxide layer 130 does not use a processing bias due to concern that ions of the HDP CVD process may bombard the liner layer 120 formed at the corners of the top surface 102 of the substrate 100 and the opening. The ion bombardment will adversely affect physical characteristics, e.g., density or thickness, of the liner layer 120 at the corners of the top surface 102 of the substrate 100. The thin region 130a of the HDP CVD oxide layer 130 is, therefore, less dense than the bulk of the HDP CVD oxide layer 130, which is formed by a HDP CVD process with a processing bias, and the pad oxide layer 110, which is formed by a thermal oxidation process.
As shown in FIG. 1B, an oxide wet etch process is then performed to remove the pad oxide layer 110. The oxide wet etch also removes portions of the liner layer 120 and the HDP CVD oxide layer 130. The remaining liner layer 120a and/or HDP CVD oxide layer 130b extend slightly over the top surface 102 of the substrate 100. As described above, the thin region 130a of the HDP CVD oxide layer 130b is less dense than the bulk of the HDP CVD oxide layer 130b and the pad oxide layer 110. The oxide wet etch process, therefore, etches the thin region 130a of the HDP CVD oxide layer 130b faster than it does the high density region, resulting in divots 140 proximate to the top surface of the thin region 130a and between the bulk of the HDP CVD oxide layer 130b and the liner layer 120a as shown in FIG. 1B. The divots can adversely affect physical profiles and/or electrical properties of the devices or circuits to be formed over the substrate 100. For example, a polysilicon layer (not shown) provided to form a transistor gate (not shown) is formed over the substrate 100 by a subsequent CVD process, filling into the divots 140. During the definition of the transistor gate, the polysilicon layer formed within the divots 140 may not be completely removed, resulting in an electrical short between two adjacent devices or circuits.
By way of background, U.S. Pat. No. 6,207,532 provides a description of methods of forming STI structures, the entirety of which is hereby incorporated by reference herein. Also, U.S. Patent Publication No. 2002/0106864 provides a description of methods for filling of a STI structure, the entirety of which is also hereby incorporated by reference herein.
From the foregoing, improved STI structures and methods of forming STI structures are desired.